[Stub] support.
Digital to analog converter header file.
DefinesFunctions
- DAC_BASE
DAC register map base address.
- DAC_CR_EN1
- DAC_CR_BOFF1
- DAC_CR_TEN1
- DAC_CR_TSEL1
- DAC_CR_WAVE1
- DAC_CR_MAMP1
- DAC_CR_DMAEN1
- DAC_CR_EN2
- DAC_CR_BOFF2
- DAC_CR_TEN2
- DAC_CR_TSEL2
- DAC_CR_WAVE2
- DAC_CR_MAMP2
- DAC_CR_DMAEN2
- DAC_SWTRIGR_SWTRIG1
- DAC_SWTRIGR_SWTRIG2
- DAC_DHR12R1_DACC1DHR
- DAC_DHR12L1_DACC1DHR
- DAC_DHR8R1_DACC1DHR
- DAC_DHR12R2_DACC2DHR
- DAC_DHR12L2_DACC2DHR
- DAC_DHR8R2_DACC2DHR
- DAC_DHR12RD_DACC1DHR
- DAC_DHR12RD_DACC2DHR
- DAC_DHR12LD_DACC1DHR
- DAC_DHR12LD_DACC2DHR
- DAC_DHR8RD_DACC1DHR
- DAC_DHR8RD_DACC2DHR
- DAC_DOR1_DACC1DOR
- DAC_DOR2_DACC2DOR
- DAC_CH1
- DAC_CH2
Variables
- const dac_dev * DAC
class dac_reg_map
DAC register map.
Public Members
- __io uint32 CR
Control register.
- __io uint32 SWTRIGR
Software trigger register.
- __io uint32 DHR12R1
Channel 1 12-bit right-aligned data holding register.
- __io uint32 DHR12L1
Channel 1 12-bit left-aligned data holding register.
- __io uint32 DHR8R1
Channel 1 8-bit left-aligned data holding register.
- __io uint32 DHR12R2
Channel 2 12-bit right-aligned data holding register.
- __io uint32 DHR12L2
Channel 2 12-bit left-aligned data holding register.
- __io uint32 DHR8R2
Channel 2 8-bit left-aligned data holding register.
- __io uint32 DHR12RD
Dual DAC 12-bit right-aligned data holding register.
- __io uint32 DHR12LD
Dual DAC 12-bit left-aligned data holding register.
- __io uint32 DHR8RD
Dual DAC 8-bit left-aligned data holding register.
- __io uint32 DOR1
Channel 1 data output register.
- __io uint32 DOR2
Channel 2 data output register.
class dac_dev
DAC device type.
Public Members
- dac_reg_map * regs
Register map.