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dma.h

Direct Memory Access (DMA) support.

Types

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doxygenstruct: Cannot find struct “dma_reg_map” in doxygen xml output for project “project0” from directory: /home/mbolivar/leaf/libmaple/doxygen/xml

struct dma_dev

DMA device type.

Public Members
struct dma_reg_map * regs

Register map.

rcc_clk_id clk_id

Clock ID.

struct dma_handler_config handlers[]

For internal use.

struct dma_handler_config

Public Members
void(* handler)(void)

nvic_irq_num irq_line

dma_mode_flags enum

Deprecated STM32F1 mode flags for dma_setup_xfer().

Use dma_tube_cfg() instead.

See:dma_tube_cfg()

Values:

  • DMA_MEM_2_MEM = 1 << 14 -

    Memory to memory mode.

  • DMA_MINC_MODE = 1 << 7 -

    Auto-increment memory address.

  • DMA_PINC_MODE = 1 << 6 -

    Auto-increment peripheral address.

  • DMA_CIRC_MODE = 1 << 5 -

    Circular mode.

  • DMA_FROM_MEM = 1 << 4 -

    Read from memory to peripheral.

  • DMA_TRNS_ERR = 1 << 3 -

    Interrupt on transfer error.

  • DMA_HALF_TRNS = 1 << 2 -

    Interrupt on half-transfer.

  • DMA_TRNS_CMPLT = 1 << 1 -

    Interrupt on transfer completion.

dma_xfer_size enum

Source and destination transfer sizes.

Use these when initializing a struct dma_tube_config.

See:

struct dma_tube_config

dma_tube_cfg

Values:

  • DMA_SIZE_8BITS = 0 -

    8-bit transfers

  • DMA_SIZE_16BITS = 1 -

    16-bit transfers

  • DMA_SIZE_32BITS = 2 -

    32-bit transfers

dma_channel enum

DMA channels.

Notes:

See:dma_tube

Values:

  • DMA_CH0 = 0 -

    Channel 0.

  • DMA_CH1 = 1 -

    Channel 1.

  • DMA_CH2 = 2 -

    Channel 2.

  • DMA_CH3 = 3 -

    Channel 3.

  • DMA_CH4 = 4 -

    Channel 4.

  • DMA_CH5 = 5 -

    Channel 5.

  • DMA_CH6 = 6 -

    Channel 6.

  • DMA_CH7 = 7 -

    Channel 7.

dma_priority enum

DMA transfer priority.

Values:

  • DMA_PRIORITY_LOW = 0 -

    Low priority.

  • DMA_PRIORITY_MEDIUM = 1 -

    Medium priority.

  • DMA_PRIORITY_HIGH = 2 -

    High priority.

  • DMA_PRIORITY_VERY_HIGH = 3 -

    Very high priority.

dma_irq_cause enum

Encodes the reason why a DMA interrupt was called.

See:dma_get_irq_cause()

Values:

  • DMA_TRANSFER_COMPLETE -

    Transfer is complete.

  • DMA_TRANSFER_HALF_COMPLETE -

    Transfer is half complete.

  • DMA_TRANSFER_ERROR -

    Error occurred during transfer.

  • DMA_TRANSFER_DME_ERROR -

    Direct mode error occurred during transfer.

  • DMA_TRANSFER_FIFO_ERROR -

    FIFO error occurred during transfer.

Warning

doxygenstruct: Cannot find struct “dma_channel_reg_map” in doxygen xml output for project “project0” from directory: /home/mbolivar/leaf/libmaple/doxygen/xml

Devices

dma_dev * DMA1

STM32F1 DMA1 device.

dma_dev * DMA2

STM32F1 DMA2 device.

Functions

void dma_init(dma_dev * dev)

Initialize a DMA device.

Parameters:
  • dev -

    Device to initialize.

void dma_setup_transfer(dma_dev * dev, dma_channel channel, __io void * peripheral_address, dma_xfer_size peripheral_size, __io void * memory_address, dma_xfer_size memory_size, uint32 mode)

Deprecated.

Use dma_tube_cfg() instead.

Set up a DMA transfer.

The channel will be disabled before being reconfigured. The transfer will have low priority by default. You may choose another priority before the transfer begins using dma_set_priority(), as well as performing any other configuration you desire. When the channel is configured to your liking, enable it using dma_enable().

Parameters:
  • dev -

    DMA device.

  • channel -

    DMA channel.

  • peripheral_address -

    Base address of peripheral data register involved in the transfer.

  • peripheral_size -

    Peripheral data transfer size.

  • memory_address -

    Base memory address involved in the transfer.

  • memory_size -

    Memory data transfer size.

  • mode -

    Logical OR of dma_mode_flags
See:

dma_tube_cfg()
Side Effects::

Disables the given DMA channel.

See:

dma_xfer_size

dma_mode_flags

dma_set_num_transfers()

dma_set_priority()

dma_attach_interrupt()

dma_enable()

void dma_set_num_transfers(dma_dev * dev, dma_channel channel, uint16 num_transfers)

void dma_set_priority(dma_dev * dev, dma_channel channel, dma_priority priority)

void dma_attach_interrupt(dma_dev * dev, dma_channel channel, void(*)(void) handler)

void dma_detach_interrupt(dma_dev * dev, dma_channel channel)

dma_irq_cause dma_get_irq_cause(dma_dev * dev, dma_channel channel)

void dma_enable(dma_dev * dev, dma_channel channel)

void dma_disable(dma_dev * dev, dma_channel channel)

void dma_set_mem_addr(dma_dev * dev, dma_tube tube, __io void * addr)

void dma_set_per_addr(dma_dev * dev, dma_channel channel, __io void * addr)

Warning

doxygenfunction: Cannot find function “dma_channel_regs” in doxygen xml output for project “project0” from directory: /home/mbolivar/leaf/libmaple/doxygen/xml

Warning

doxygenfunction: Cannot find function “dma_is_channel_enabled” in doxygen xml output for project “project0” from directory: /home/mbolivar/leaf/libmaple/doxygen/xml

uint8 dma_get_isr_bits(dma_dev * dev, dma_tube tube)

void dma_clear_isr_bits(dma_dev * dev, dma_tube tube)

Register Map Base Pointers

DMA1_BASE

DMA controller 1 register map base pointer.

DMA2_BASE

DMA controller 2 register map base pointer.

Register Bit Definitions

Interrupt status register

DMA_ISR_TEIF7_BIT

DMA_ISR_HTIF7_BIT

DMA_ISR_TCIF7_BIT

DMA_ISR_GIF7_BIT

DMA_ISR_TEIF6_BIT

DMA_ISR_HTIF6_BIT

DMA_ISR_TCIF6_BIT

DMA_ISR_GIF6_BIT

DMA_ISR_TEIF5_BIT

DMA_ISR_HTIF5_BIT

DMA_ISR_TCIF5_BIT

DMA_ISR_GIF5_BIT

DMA_ISR_TEIF4_BIT

DMA_ISR_HTIF4_BIT

DMA_ISR_TCIF4_BIT

DMA_ISR_GIF4_BIT

DMA_ISR_TEIF3_BIT

DMA_ISR_HTIF3_BIT

DMA_ISR_TCIF3_BIT

DMA_ISR_GIF3_BIT

DMA_ISR_TEIF2_BIT

DMA_ISR_HTIF2_BIT

DMA_ISR_TCIF2_BIT

DMA_ISR_GIF2_BIT

DMA_ISR_TEIF1_BIT

DMA_ISR_HTIF1_BIT

DMA_ISR_TCIF1_BIT

DMA_ISR_GIF1_BIT

DMA_ISR_TEIF7

DMA_ISR_HTIF7

DMA_ISR_TCIF7

DMA_ISR_GIF7

DMA_ISR_TEIF6

DMA_ISR_HTIF6

DMA_ISR_TCIF6

DMA_ISR_GIF6

DMA_ISR_TEIF5

DMA_ISR_HTIF5

DMA_ISR_TCIF5

DMA_ISR_GIF5

DMA_ISR_TEIF4

DMA_ISR_HTIF4

DMA_ISR_TCIF4

DMA_ISR_GIF4

DMA_ISR_TEIF3

DMA_ISR_HTIF3

DMA_ISR_TCIF3

DMA_ISR_GIF3

DMA_ISR_TEIF2

DMA_ISR_HTIF2

DMA_ISR_TCIF2

DMA_ISR_GIF2

DMA_ISR_TEIF1

DMA_ISR_HTIF1

DMA_ISR_TCIF1

DMA_ISR_GIF1

Interrupt flag clear register

DMA_IFCR_CTEIF7_BIT

DMA_IFCR_CHTIF7_BIT

DMA_IFCR_CTCIF7_BIT

DMA_IFCR_CGIF7_BIT

DMA_IFCR_CTEIF6_BIT

DMA_IFCR_CHTIF6_BIT

DMA_IFCR_CTCIF6_BIT

DMA_IFCR_CGIF6_BIT

DMA_IFCR_CTEIF5_BIT

DMA_IFCR_CHTIF5_BIT

DMA_IFCR_CTCIF5_BIT

DMA_IFCR_CGIF5_BIT

DMA_IFCR_CTEIF4_BIT

DMA_IFCR_CHTIF4_BIT

DMA_IFCR_CTCIF4_BIT

DMA_IFCR_CGIF4_BIT

DMA_IFCR_CTEIF3_BIT

DMA_IFCR_CHTIF3_BIT

DMA_IFCR_CTCIF3_BIT

DMA_IFCR_CGIF3_BIT

DMA_IFCR_CTEIF2_BIT

DMA_IFCR_CHTIF2_BIT

DMA_IFCR_CTCIF2_BIT

DMA_IFCR_CGIF2_BIT

DMA_IFCR_CTEIF1_BIT

DMA_IFCR_CHTIF1_BIT

DMA_IFCR_CTCIF1_BIT

DMA_IFCR_CGIF1_BIT

DMA_IFCR_CTEIF7

DMA_IFCR_CHTIF7

DMA_IFCR_CTCIF7

DMA_IFCR_CGIF7

DMA_IFCR_CTEIF6

DMA_IFCR_CHTIF6

DMA_IFCR_CTCIF6

DMA_IFCR_CGIF6

DMA_IFCR_CTEIF5

DMA_IFCR_CHTIF5

DMA_IFCR_CTCIF5

DMA_IFCR_CGIF5

DMA_IFCR_CTEIF4

DMA_IFCR_CHTIF4

DMA_IFCR_CTCIF4

DMA_IFCR_CGIF4

DMA_IFCR_CTEIF3

DMA_IFCR_CHTIF3

DMA_IFCR_CTCIF3

DMA_IFCR_CGIF3

DMA_IFCR_CTEIF2

DMA_IFCR_CHTIF2

DMA_IFCR_CTCIF2

DMA_IFCR_CGIF2

DMA_IFCR_CTEIF1

DMA_IFCR_CHTIF1

DMA_IFCR_CTCIF1

DMA_IFCR_CGIF1

Channel configuration register

DMA_CCR_MEM2MEM_BIT

DMA_CCR_MINC_BIT

DMA_CCR_PINC_BIT

DMA_CCR_CIRC_BIT

DMA_CCR_DIR_BIT

DMA_CCR_TEIE_BIT

DMA_CCR_HTIE_BIT

DMA_CCR_TCIE_BIT

DMA_CCR_EN_BIT

DMA_CCR_MEM2MEM

DMA_CCR_PL

DMA_CCR_PL_LOW

DMA_CCR_PL_MEDIUM

DMA_CCR_PL_HIGH

DMA_CCR_PL_VERY_HIGH

DMA_CCR_MSIZE

DMA_CCR_MSIZE_8BITS

DMA_CCR_MSIZE_16BITS

DMA_CCR_MSIZE_32BITS

DMA_CCR_PSIZE

DMA_CCR_PSIZE_8BITS

DMA_CCR_PSIZE_16BITS

DMA_CCR_PSIZE_32BITS

DMA_CCR_MINC

DMA_CCR_PINC

DMA_CCR_CIRC

DMA_CCR_DIR

DMA_CCR_TEIE

DMA_CCR_HTIE

DMA_CCR_TCIE

DMA_CCR_EN

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© Copyright 2010, 2011, LeafLabs, LLC. Last updated on Sep 05, 2012. Created using Sphinx 1.1.3.