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gpio.h

General Purpose Input/Output (GPIO) port and Alternate Function Input/Output (AFIO) support.

Types

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struct gpio_dev

GPIO device type.

Public Members
gpio_reg_map * regs

Register map.

rcc_clk_id clk_id

RCC clock information.

exti_cfg exti_port

(Deprecated) External interrupt port.

Instead of dev->exti_port, use gpio_exti_port(dev).

gpio_pin_mode enum

GPIO pin modes.

These only allow for 50MHZ max output speeds; if you want slower, use direct register access.

Values:

  • GPIO_OUTPUT_PP = GPIO_CR_CNF_OUTPUT_PP | GPIO_CR_MODE_OUTPUT_50MHZ -

    Output push-pull.

  • GPIO_OUTPUT_OD = GPIO_CR_CNF_OUTPUT_OD | GPIO_CR_MODE_OUTPUT_50MHZ -

    Output open-drain.

  • GPIO_AF_OUTPUT_PP = GPIO_CR_CNF_AF_OUTPUT_PP | GPIO_CR_MODE_OUTPUT_50MHZ -

    Alternate function output push-pull.

  • GPIO_AF_OUTPUT_OD = GPIO_CR_CNF_AF_OUTPUT_OD | GPIO_CR_MODE_OUTPUT_50MHZ -

    Alternate function output open drain.

  • GPIO_INPUT_ANALOG = GPIO_CR_CNF_INPUT_ANALOG | GPIO_CR_MODE_INPUT -

    Analog input.

  • GPIO_INPUT_FLOATING = GPIO_CR_CNF_INPUT_FLOATING | GPIO_CR_MODE_INPUT -

    Input floating.

  • GPIO_INPUT_PD = GPIO_CR_CNF_INPUT_PU_PD | GPIO_CR_MODE_INPUT -

    Input pull-down.

  • GPIO_INPUT_PU -

    Input pull-up.

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doxygenstruct: Cannot find struct “afio_reg_map” in doxygen xml output for project “project0” from directory: /home/mbolivar/leaf/libmaple/doxygen/xml

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doxygenenum: Cannot find enum “afio_exti_port” in doxygen xml output for project “project0” from directory: /home/mbolivar/leaf/libmaple/doxygen/xml

Warning

doxygenenum: Cannot find enum “afio_exti_num” in doxygen xml output for project “project0” from directory: /home/mbolivar/leaf/libmaple/doxygen/xml

afio_remap_peripheral enum

Available peripheral remaps.

See:afio_remap()

Values:

  • AFIO_REMAP_ADC2_ETRGREG = AFIO_MAPR_ADC2_ETRGREG_REMAP -

    ADC 2 external trigger regular conversion remapping.

  • AFIO_REMAP_ADC2_ETRGINJ = AFIO_MAPR_ADC2_ETRGINJ_REMAP -

    ADC 2 external trigger injected conversion remapping.

  • AFIO_REMAP_ADC1_ETRGREG = AFIO_MAPR_ADC1_ETRGREG_REMAP -

    ADC 1 external trigger regular conversion remapping.

  • AFIO_REMAP_ADC1_ETRGINJ = AFIO_MAPR_ADC1_ETRGINJ_REMAP -

    ADC 1 external trigger injected conversion remapping.

  • AFIO_REMAP_TIM5CH4_I = AFIO_MAPR_TIM5CH4_IREMAP -

    Timer 5 channel 4 internal remapping.

  • AFIO_REMAP_PD01 = AFIO_MAPR_PD01_REMAP -

    Port D0/Port D1 mapping on OSC_IN/OSC_OUT.

  • AFIO_REMAP_CAN_1 = AFIO_MAPR_CAN_REMAP_PB8_PB9 -

    CAN alternate function remapping 1 (RX on PB8, TX on PB9)

  • AFIO_REMAP_CAN_2 = AFIO_MAPR_CAN_REMAP_PD0_PD1 -

    CAN alternate function remapping 2 (RX on PD0, TX on PD1)

  • AFIO_REMAP_TIM4 = AFIO_MAPR_TIM4_REMAP -

    Timer 4 remapping.

  • AFIO_REMAP_TIM3_PARTIAL = AFIO_MAPR_TIM3_REMAP_PARTIAL -

    Timer 3 partial remapping.

  • AFIO_REMAP_TIM3_FULL = AFIO_MAPR_TIM3_REMAP_FULL -

    Timer 3 full remapping.

  • AFIO_REMAP_TIM2_PARTIAL_1 = AFIO_MAPR_TIM2_REMAP_PA15_PB3_PA2_PA3 -

    Timer 2 partial remapping 1 (CH1 and ETR on PA15, CH2 on PB3, CH3 on PA2, CH4 on PA3)

  • AFIO_REMAP_TIM2_PARTIAL_2 = AFIO_MAPR_TIM2_REMAP_PA0_PA1_PB10_PB11 -

    Timer 2 partial remapping 2 (CH1 and ETR on PA0, CH2 on PA1, CH3 on PB10, CH4 on PB11)

  • AFIO_REMAP_TIM2_FULL = AFIO_MAPR_TIM2_REMAP_FULL -

    Timer 2 full remapping.

  • AFIO_REMAP_USART2 = AFIO_MAPR_USART2_REMAP -

    USART 2 remapping.

  • AFIO_REMAP_USART1 = AFIO_MAPR_USART1_REMAP -

    USART 1 remapping.

  • AFIO_REMAP_I2C1 = AFIO_MAPR_I2C1_REMAP -

    I2C 1 remapping.

  • AFIO_REMAP_SPI1 = AFIO_MAPR_SPI1_REMAP -

    SPI 1 remapping.

  • AFIO_REMAP_FSMC_NADV = AFIO_MAPR2_FSMC_NADV | AFIO_REMAP_USE_MAPR2 -

    NADV signal not connected.

  • AFIO_REMAP_TIM14 = AFIO_MAPR2_TIM14_REMAP | AFIO_REMAP_USE_MAPR2 -

    Timer 14 remapping.

  • AFIO_REMAP_TIM13 = AFIO_MAPR2_TIM13_REMAP | AFIO_REMAP_USE_MAPR2 -

    Timer 13 remapping.

  • AFIO_REMAP_TIM11 = AFIO_MAPR2_TIM11_REMAP | AFIO_REMAP_USE_MAPR2 -

    Timer 11 remapping.

  • AFIO_REMAP_TIM10 = AFIO_MAPR2_TIM10_REMAP | AFIO_REMAP_USE_MAPR2 -

    Timer 10 remapping.

  • AFIO_REMAP_TIM9 = AFIO_MAPR2_TIM9_REMAP | AFIO_REMAP_USE_MAPR2 -

    Timer 9 remapping.

afio_debug_cfg enum

Debug port configuration.

Used to configure the behavior of JTAG and Serial Wire (SW) debug ports and their associated GPIO pins.

See:afio_cfg_debug_ports()

Values:

  • AFIO_DEBUG_FULL_SWJ = AFIO_MAPR_SWJ_CFG_FULL_SWJ -

    Full Serial Wire and JTAG debug.

  • AFIO_DEBUG_FULL_SWJ_NO_NJRST = AFIO_MAPR_SWJ_CFG_FULL_SWJ_NO_NJRST -

    Full Serial Wire and JTAG, but no NJTRST.

  • AFIO_DEBUG_SW_ONLY = AFIO_MAPR_SWJ_CFG_NO_JTAG_SW -

    Serial Wire debug only (JTAG-DP disabled, SW-DP enabled)

  • AFIO_DEBUG_NONE = AFIO_MAPR_SWJ_CFG_NO_JTAG_NO_SW -

    No debug; all JTAG and SW pins are free for use as GPIOs.

Devices

struct gpio_dev *const GPIOA

GPIO port A device.

struct gpio_dev *const GPIOB

GPIO port B device.

struct gpio_dev *const GPIOC

GPIO port C device.

struct gpio_dev *const GPIOD

GPIO port D device.

struct gpio_dev *const GPIOE

GPIO port E device.

struct gpio_dev *const GPIOF

GPIO port F device.

struct gpio_dev *const GPIOG

GPIO port G device.

Functions

void gpio_init(gpio_dev * dev)

Initialize a GPIO device.

Enables the clock for and resets the given device.

Parameters:
  • dev -

    GPIO device to initialize.

void gpio_init_all(void)

Initialize and reset all available GPIO devices.

void gpio_set_mode(struct gpio_dev * dev, uint8 bit, gpio_pin_mode mode)

Set the mode of a GPIO pin.

Calling this function is equivalent to calling gpio_set_modef(dev, pin, mode, GPIO_MODE_SPEED_HIGH). Note that this overrides the default speed.

Parameters:
  • dev -

    GPIO device.

  • bit -

    Bit on the device whose mode to set, 0–15.

  • mode -

    Mode to set the pin to.

exti_cfg gpio_exti_port(gpio_dev * dev)

Get a GPIO port’s corresponding EXTI port configuration.

Parameters:
  • dev -

    GPIO port whose exti_cfg to return.

void gpio_write_bit(gpio_dev * dev, uint8 pin, uint8 val)

Set or reset a GPIO pin.

Pin must have previously been configured to output mode.

Parameters:
  • dev -

    GPIO device whose pin to set.

  • pin -

    Pin on to set or reset

  • val -

    If true, set the pin. If false, reset the pin.

uint32 gpio_read_bit(gpio_dev * dev, uint8 pin)

Determine whether or not a GPIO pin is set.

Pin must have previously been configured to input mode.

Parameters:
  • dev -

    GPIO device whose pin to test.

  • pin -

    Pin on dev to test.

Return:

True if the pin is set, false otherwise.

void gpio_toggle_bit(gpio_dev * dev, uint8 pin)

Toggle a pin configured as output push-pull.

Parameters:
  • dev -

    GPIO device.

  • pin -

    Pin on dev to toggle.

void afio_init(void)

Initialize the AFIO clock, and reset the AFIO registers.

void afio_exti_select(exti_num exti, exti_cfg port)

Deprecated.

Use exti_select(exti, port) instead.

void afio_remap(afio_remap_peripheral p)

void afio_cfg_debug_ports(afio_debug_cfg config)

Enable or disable the JTAG and SW debug ports.

Parameters:
  • config -

    Desired debug port configuration

See:

afio_debug_cfg

Register Map Base Pointers

GPIOA_BASE

GPIO port A register map base pointer.

GPIOB_BASE

GPIO port B register map base pointer.

GPIOC_BASE

GPIO port C register map base pointer.

GPIOD_BASE

GPIO port D register map base pointer.

GPIOE_BASE

GPIO port E register map base pointer.

GPIOF_BASE

GPIO port F register map base pointer.

GPIOG_BASE

GPIO port G register map base pointer.

AFIO_BASE

AFIO register map base pointer.

Register Bit Definitions

GPIO Control Registers

These values apply to both the low and high configuration registers (ST RM0008: GPIOx_CRL and GPIOx_CRH). You can shift them right by the appropriate number of bits for the GPIO port bit you’re interested in to obtain a bit mask.

For example, to mask out just the value of GPIOA_CRH_CNF12, note that GPIO port bit 12’s configuration starts at bit 18 in the corresponding CRH. Thus, an appropriate mask is GPIOA_BASE->CRH & (GPIO_CR_CNF << 18).

GPIO_CR_CNF_INPUT_ANALOG

GPIO_CR_CNF_INPUT_FLOATING

GPIO_CR_CNF_INPUT_PU_PD

GPIO_CR_CNF_OUTPUT_PP

GPIO_CR_CNF_OUTPUT_OD

GPIO_CR_CNF_AF_OUTPUT_PP

GPIO_CR_CNF_AF_OUTPUT_OD

GPIO_CR_MODE_INPUT

GPIO_CR_MODE_OUTPUT_10MHZ

GPIO_CR_MODE_OUTPUT_2MHZ

GPIO_CR_MODE_OUTPUT_50MHZ

Event Control Register

AFIO_EVCR_EVOE

AFIO_EVCR_PORT_PA

AFIO_EVCR_PORT_PB

AFIO_EVCR_PORT_PC

AFIO_EVCR_PORT_PD

AFIO_EVCR_PORT_PE

AFIO_EVCR_PIN_0

AFIO_EVCR_PIN_1

AFIO_EVCR_PIN_2

AFIO_EVCR_PIN_3

AFIO_EVCR_PIN_4

AFIO_EVCR_PIN_5

AFIO_EVCR_PIN_6

AFIO_EVCR_PIN_7

AFIO_EVCR_PIN_8

AFIO_EVCR_PIN_9

AFIO_EVCR_PIN_10

AFIO_EVCR_PIN_11

AFIO_EVCR_PIN_12

AFIO_EVCR_PIN_13

AFIO_EVCR_PIN_14

AFIO_EVCR_PIN_15

AF Remap and Debug I/O Configuration Register

AFIO_MAPR_SWJ_CFG

AFIO_MAPR_SWJ_CFG_FULL_SWJ

AFIO_MAPR_SWJ_CFG_FULL_SWJ_NO_NJRST

AFIO_MAPR_SWJ_CFG_NO_JTAG_SW

AFIO_MAPR_SWJ_CFG_NO_JTAG_NO_SW

AFIO_MAPR_ADC2_ETRGREG_REMAP

AFIO_MAPR_ADC2_ETRGINJ_REMAP

AFIO_MAPR_ADC1_ETRGREG_REMAP

AFIO_MAPR_ADC1_ETRGINJ_REMAP

AFIO_MAPR_TIM5CH4_IREMAP

AFIO_MAPR_PD01_REMAP

AFIO_MAPR_CAN_REMAP

AFIO_MAPR_CAN_REMAP_NONE

AFIO_MAPR_CAN_REMAP_PB8_PB9

AFIO_MAPR_CAN_REMAP_PD0_PD1

AFIO_MAPR_TIM4_REMAP

AFIO_MAPR_TIM3_REMAP

AFIO_MAPR_TIM3_REMAP_NONE

AFIO_MAPR_TIM3_REMAP_PARTIAL

AFIO_MAPR_TIM3_REMAP_FULL

AFIO_MAPR_TIM2_REMAP

AFIO_MAPR_TIM2_REMAP_NONE

AFIO_MAPR_TIM2_REMAP_PA15_PB3_PA2_PA3

AFIO_MAPR_TIM2_REMAP_PA0_PA1_PB10_PB11

AFIO_MAPR_TIM2_REMAP_FULL

AFIO_MAPR_TIM1_REMAP

AFIO_MAPR_TIM1_REMAP_NONE

AFIO_MAPR_TIM1_REMAP_PARTIAL

AFIO_MAPR_TIM1_REMAP_FULL

AFIO_MAPR_USART3_REMAP

AFIO_MAPR_USART3_REMAP_NONE

AFIO_MAPR_USART3_REMAP_PARTIAL

AFIO_MAPR_USART3_REMAP_FULL

AFIO_MAPR_USART2_REMAP

AFIO_MAPR_USART1_REMAP

AFIO_MAPR_I2C1_REMAP

AFIO_MAPR_SPI1_REMAP

External Interrupt Configuration Register 1

AFIO_EXTICR1_EXTI3

AFIO_EXTICR1_EXTI3_PA

AFIO_EXTICR1_EXTI3_PB

AFIO_EXTICR1_EXTI3_PC

AFIO_EXTICR1_EXTI3_PD

AFIO_EXTICR1_EXTI3_PE

AFIO_EXTICR1_EXTI3_PF

AFIO_EXTICR1_EXTI3_PG

AFIO_EXTICR1_EXTI2

AFIO_EXTICR1_EXTI2_PA

AFIO_EXTICR1_EXTI2_PB

AFIO_EXTICR1_EXTI2_PC

AFIO_EXTICR1_EXTI2_PD

AFIO_EXTICR1_EXTI2_PE

AFIO_EXTICR1_EXTI2_PF

AFIO_EXTICR1_EXTI2_PG

AFIO_EXTICR1_EXTI1

AFIO_EXTICR1_EXTI1_PA

AFIO_EXTICR1_EXTI1_PB

AFIO_EXTICR1_EXTI1_PC

AFIO_EXTICR1_EXTI1_PD

AFIO_EXTICR1_EXTI1_PE

AFIO_EXTICR1_EXTI1_PF

AFIO_EXTICR1_EXTI1_PG

AFIO_EXTICR1_EXTI0

AFIO_EXTICR1_EXTI0_PA

AFIO_EXTICR1_EXTI0_PB

AFIO_EXTICR1_EXTI0_PC

AFIO_EXTICR1_EXTI0_PD

AFIO_EXTICR1_EXTI0_PE

AFIO_EXTICR1_EXTI0_PF

AFIO_EXTICR1_EXTI0_PG

External Interrupt Configuration Register 2

AFIO_EXTICR2_EXTI7

AFIO_EXTICR2_EXTI7_PA

AFIO_EXTICR2_EXTI7_PB

AFIO_EXTICR2_EXTI7_PC

AFIO_EXTICR2_EXTI7_PD

AFIO_EXTICR2_EXTI7_PE

AFIO_EXTICR2_EXTI7_PF

AFIO_EXTICR2_EXTI7_PG

AFIO_EXTICR2_EXTI6

AFIO_EXTICR2_EXTI6_PA

AFIO_EXTICR2_EXTI6_PB

AFIO_EXTICR2_EXTI6_PC

AFIO_EXTICR2_EXTI6_PD

AFIO_EXTICR2_EXTI6_PE

AFIO_EXTICR2_EXTI6_PF

AFIO_EXTICR2_EXTI6_PG

AFIO_EXTICR2_EXTI5

AFIO_EXTICR2_EXTI5_PA

AFIO_EXTICR2_EXTI5_PB

AFIO_EXTICR2_EXTI5_PC

AFIO_EXTICR2_EXTI5_PD

AFIO_EXTICR2_EXTI5_PE

AFIO_EXTICR2_EXTI5_PF

AFIO_EXTICR2_EXTI5_PG

AFIO_EXTICR2_EXTI4

AFIO_EXTICR2_EXTI4_PA

AFIO_EXTICR2_EXTI4_PB

AFIO_EXTICR2_EXTI4_PC

AFIO_EXTICR2_EXTI4_PD

AFIO_EXTICR2_EXTI4_PE

AFIO_EXTICR2_EXTI4_PF

AFIO_EXTICR2_EXTI4_PG

AF Remap and Debug I/O Configuration Register 2

AFIO_MAPR2_FSMC_NADV

AFIO_MAPR2_TIM14_REMAP

AFIO_MAPR2_TIM13_REMAP

AFIO_MAPR2_TIM11_REMAP

AFIO_MAPR2_TIM10_REMAP

AFIO_MAPR2_TIM9_REMAP

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© Copyright 2010, 2011, LeafLabs, LLC. Last updated on Sep 05, 2012. Created using Sphinx 1.1.3.