<libmaple/iwdg.h>

Independent Watchdog (IWDG) support. The IWDG peripheral is common across supported targets, so everything documented here is portable.

Usage Note

To use the independent watchdog, first call iwdg_init() with the appropriate prescaler and IWDG counter reload values for your application. Afterwards, you must periodically call iwdg_feed() before the IWDG counter reaches zero to reset the counter to its reload value. If you do not, the chip will reset.

Once started, the independent watchdog cannot be turned off.

Devices

None at this time.

Functions

void iwdg_init(iwdg_prescaler prescaler, uint16 reload)

Initialise and start the watchdog.

The prescaler and reload set the timeout. For example, a prescaler of IWDG_PRE_32 divides the 40 kHz clock by 32 and gives roughly 1 ms per reload.

Parameters:

• prescaler -

  Prescaler for the 40 kHz IWDG clock.

• reload -

  Independent watchdog counter reload value.

void iwdg_feed(void)

Reset the IWDG counter.

Calling this function will cause the IWDG counter to be reset to its reload value.

Types

iwdg_prescaler enum

Independent watchdog prescalers.

These divide the 40 kHz IWDG clock.

Values:

• IWDG_PRE_4 = IWDG_PR_DIV_4 -

  Divide by 4.

• IWDG_PRE_8 = IWDG_PR_DIV_8 -

  Divide by 8.

• IWDG_PRE_16 = IWDG_PR_DIV_16 -

  Divide by 16.

• IWDG_PRE_32 = IWDG_PR_DIV_32 -

  Divide by 32.

• IWDG_PRE_64 = IWDG_PR_DIV_64 -

  Divide by 64.

• IWDG_PRE_128 = IWDG_PR_DIV_128 -

  Divide by 128.

• IWDG_PRE_256 = IWDG_PR_DIV_256 -

  Divide by 256.

Register Maps

IWDG_BASE

Independent watchdog base pointer.

struct iwdg_reg_map

Independent watchdog register map type.

Public Members

__io uint32 KR

Key register.

__io uint32 PR

Prescaler register.

__io uint32 RLR

Reload register.

__io uint32 SR

Status register.

Register Bit Definitions

These are given as source code.

/* Key register */

#define IWDG_KR_UNLOCK                  0x5555
#define IWDG_KR_FEED                    0xAAAA
#define IWDG_KR_START                   0xCCCC

/* Prescaler register */

#define IWDG_PR_DIV_4                   0x0
#define IWDG_PR_DIV_8                   0x1
#define IWDG_PR_DIV_16                  0x2
#define IWDG_PR_DIV_32                  0x3
#define IWDG_PR_DIV_64                  0x4
#define IWDG_PR_DIV_128                 0x5
#define IWDG_PR_DIV_256                 0x6

/* Status register */

#define IWDG_SR_RVU_BIT                 1
#define IWDG_SR_PVU_BIT                 0

#define IWDG_SR_RVU                     (1U << IWDG_SR_RVU_BIT)
#define IWDG_SR_PVU                     (1U << IWDG_SR_PVU_BIT)