Universal Synchronous/Asynchronous Receiver/Transmitter (USART, or commonly serial port) support.
Contents
USART register map type.
Public Members
- __io uint32 SR
Status register.
- __io uint32 DR
Data register.
- __io uint32 BRR
Baud rate register.
- __io uint32 CR1
Control register 1.
- __io uint32 CR2
Control register 2.
- __io uint32 CR3
Control register 3.
- __io uint32 GTPR
Guard time and prescaler register.
USART device type.
Public Members
- usart_reg_map * regs
Register map.
- ring_buffer * rb
RX ring buffer.
- uint32 max_baud
Deprecated.
Maximum baud rate.
- uint8 rx_buf[USART_RX_BUF_SIZE]
Deprecated.
Actual RX buffer used by rb. This field will be removed in a future release.
- rcc_clk_id clk_id
RCC clock information.
- nvic_irq_num irq_num
USART NVIC interrupt.
USART1 device.
USART2 device.
USART3 device.
UART4 device.
UART5 device.
Initialize a serial port.
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Enable a serial port.
USART is enabled in single buffer transmission mode, multibuffer receiver mode, 8n1.
Serial port must have a baud rate configured to work properly.
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See: | usart_set_baud_rate() |
Turn off a serial port.
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Disable all serial ports.
Nonblocking USART receive.
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Return: | Number of bytes received |
Nonblocking USART transmit.
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Return: | Number of bytes transmitted |
Transmit an unsigned integer to the specified serial port in decimal format.
This function blocks until the integer’s digits have been completely transmitted.
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Transmit one character on a serial port.
This function blocks until the character has been successfully transmitted.
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Transmit a character string on a serial port.
This function blocks until str is completely transmitted.
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Read one character from a serial port.
It’s not safe to call this function if the serial port has no data available.
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Return: | byte read |
See: |
Return the amount of data available in a serial port’s RX buffer.
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Return: | Number of bytes in dev’s RX buffer. |
Discard the contents of a serial port’s RX buffer.
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USART1 register map base pointer.
USART2 register map base pointer.
USART3 register map base pointer.
UART4 register map base pointer.
UART5 register map base pointer.
Clear to send bit.
Line break detection bit.
Transmit data register empty bit.
Transmission complete bit.
Read data register not empty bit.
IDLE line detected bit.
Overrun error bit.
Noise error bit.
Framing error bit.
Parity error bit.
Clear to send mask.
Line break detected mask.
Transmit data register empty mask.
Transmission complete mask.
Read data register not empty mask.
IDLE line detected mask.
Overrun error mask.
Noise error mask.
Framing error mask.
Parity error mask.
Data register data value mask.
Mantissa of USARTDIV mask.
Fraction of USARTDIV mask.
USART enable bit.
Word length bit.
Wakeup method bit.
Parity control enable bit.
Parity selection bit.
Parity error interrupt enable bit.
Transmit data regsiter not empty interrupt enable bit.
Transmission complete interrupt enable bit.
RXNE interrupt enable bit.
IDLE interrupt enable bit.
Transmitter enable bit.
Receiver enable bit.
Receiver wakeup bit.
Send break bit.
USART enable mask.
Word length mask.
Wakeup method mask.
Wakeup on idle line.
Wakeup on address mark.
Parity control enable mask.
Parity selection mask.
Parity selection: even parity.
Parity selection: odd parity.
Parity error interrupt enable mask.
Transmit data register empty interrupt enable mask.
Transmission complete interrupt enable mask.
RXNE interrupt enable mask.
IDLE line interrupt enable mask.
Transmitter enable mask.
Receiver enable mask.
Receiver wakeup mask.
Receiver wakeup: receiver in active mode.
Receiver wakeup: receiver in mute mode.
Send break.
LIN mode enable bit.
Clock enable bit.
Clock polarity bit.
Clock phase bit.
Last bit clock pulse bit.
LIN break detection interrupt enable bit.
LIN break detection length bit.
LIN mode enable mask.
STOP bits mask.
STOP bits: 1 stop bit.
STOP bits: 0.5 stop bits Not available on UART4, UART5.
STOP bits: 1.5 stop bits Not available on UART4, UART5.
STOP bits: 2 stop bits.
Clock enable.
Not available on UART4, UART5
Clock polarity mask.
Not available on UART4, UART5
Clock polarity: low.
Clock polarity: high.
Clock phase mask.
Not available on UART4, UART5
Clock phase: first First clock transition is the first data capture edge.
Clock phase: second Second clock transition is the first data capture edge.
Last bit clock pulse mask.
When set, the last bit transmitted causes a clock pulse in synchronous mode.
Not available on UART4, UART5
LIN break detection interrupt enable mask.
LIN break detection length.
LIN break detection length: 10 bits.
LIN break detection length: 11 bits.
Address of the USART node This is useful during multiprocessor communication.
Clear to send interrupt enable bit.
Clear to send enable bit.
Ready to send enable bit.
DMA enable transmitter bit.
DMA enable receiver bit.
Smartcard mode enable bit.
Smartcard NACK enable bit.
Half-duplex selection bit.
IrDA low power bit.
IrDA mode enable bit.
Error interrupt enable bit.
Clear to send interrupt enable Not available on UART4, UART5.
Clear to send enable Not available on UART4, UART5.
Ready to send enable Not available on UART4, UART5.
DMA enable transmitter Not available on UART5.
DMA enable receiver Not available on UART5.
Smartcard mode enable Not available on UART4, UART5.
Smartcard NACK enable Not available on UART4, UART5.
Half-duplex selection When set, single-wire half duplex mode is selected.
IrDA low power mode.
IrDA mode: normal.
IrDA mode: low power.
IrDA mode enable.
Error interrupt enable.
Guard time value mask Used in Smartcard mode.
Not available on UART4, UART5.
Prescaler value mask Restrictions on this value apply, depending on the USART mode.
Not available on UART4, UART5.